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mt9t001 - 1/2-inch 3-megapixel digital image sensor features 81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_1.fm - rev. d 7/05 en 1 ?2004 micron technology, inc. all rights reserved. products and specifications discussed herein are for subject to change by micron without notice. 1/2-inch 3-megapixel cmos digital image sensor MT9T001P12STC for the latest data sheet, refer to micron?s web site: www.micron.com/imaging features ? digitalclarity? image sensor technology ?high frame rate ? global reset release ? horizontal and vertical binning ?column and row skip modes ? superior low-light performance ?low dark current ? simple two-wire serial interface ? programmable controls: gain, frame rate, frame size, exposure ? pin-for-pin compatible with micron?s 1.3-megapixel mt9m001 and 2-megapixel mt9d001 applications ? digital still cameras ? digital video cameras ? converged dscs/camcorders general description the micron ? imaging mt9t001 is a qxga-format 1/2- inch cmos active-pixel digital image sensor with an active imaging pixe l array of 2,048h x 1,536v. it incor- porates sophisticated camera functions on-chip such as windowing, column and row skip mode, and snap- shot mode. it is programmable through a simple two- wire serial interface. the 3-megapixel cmos image sensor features digital- clarity?micron?s breakthrough low-noise cmos imaging technology that achieves ccd image quality (based on signal-to-noise ratio and low-light sensitiv- ity) while maintaining the inherent size, cost, and inte- gration advantages of cmos. the sensor can be operated in its default mode or pro- grammed by the user for frame size, exposure, gain set- ting, and other parameters. the default mode outputs a qxga image at 12 frames per second (fps). an on- chip analog-to-digital conver ter (adc) provides 10 bits per pixel. frame_valid and line_valid signals are output on dedicated pins, al ong with a pixel clock that is synchronous with valid data. table 1: key performance parameters the mt9t001 produces extraordinarily clear, sharp digital pictures, and its ability to capture both continu- ous video and single frames makes it the perfect choice for a wide range of consumer and industrial applica- tions, including digital still cameras, digital video cam- eras, and pc cameras. parameter typical value optical format 1/2-inch (4:3) active imager size 6.55mm(h) x 4.92mm(v) 8.19 (diagonal) active pixels 2,048h x 1,536v pixel size 3.2 m x 3.2 m color filter arra y rgb bayer pattern shutter type global re set release (grr), electronic rolling shutter (ers) maximum data rate/ master clock 48 mps/48 mhz frame rate qxga (2,048 x 1,536) programmable up to 12 fps uxga (1,600 x 1,200) programmable up to 20 fps sxga (1,280 x 1,024) programmable up to 27 fps xga (1,024 x 768) programmable up to 43 fps vga (640 x 480) programmable up to 93 fps adc resolution 10-bit, on-chip responsivity >1.0 v/lux-sec (550nm) dynamic range 61db snr max 43db supply voltage 3.0v ? 3.6v (3.3v nominal) power consumption 240mw (nominal); 2w (standby) operating temperature 0c to +60c packaging 48-pin plcc
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_dstoc.fm - rev. d 7/05 en 2 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description (continued). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 pixel data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 pixel array structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 output data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 output data timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 frame timing formulas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 feature description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 window control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 window size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 electronic panning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 blanking control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 frame time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 high frame rate readout modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 pixel integration time control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 snapshot mode and flash control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 setting up for snapshot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 triggering a snapshot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 strobe pulse output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 global shutter release sn apshot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 programmed exposure mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 bulb mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 skip and bin modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 smaller format resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 line_valid formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 signal path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 gain settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 black level calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 manual black level calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 black level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 standby control and chip enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 serial bus description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 bus idle state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 start bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 stop bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 slave address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 data bit transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 acknowledge bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 no-acknowledge bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 two-wire serial interface sample write and read sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 16-bit write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 16-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 data output and propagation delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_dstoc.fm - rev. d 7/05 en 3 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor table of contents two-wire serial bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 rev d, 06/2005 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 rev c, preliminary 09/2004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 rev b, preliminary 03/2004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 rev a, verion 1.0, preliminary 12/2003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_dslof.fm - rev. d 7/05 en 4 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor list of figures list of figures figure 1: block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 2: typical configuration (connection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 3: pinout-48-pin plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 4: pixel array description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 5: pixel color pattern detail (top ri ght corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 6: spatial illustration of image re adout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 7: timing example of pixel data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 8: row timing and frame_valid/line_valid signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 9: windowing capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 10: windowing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 11: column skip 2x; row skip 2x enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 12: column skip 3x; row skip 3x enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 13: column skip 4x; row skip 4x enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 14: column skip 8x; row skip 8x enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 15: bin 2-to-1: 2,048h x 1,536v (qxga) to 1,024h x 768v (xga) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 16: bin 3-to-1: 2,048h x 1,536v (qxga) to 640h x 480v (vga) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 17: different line_valid formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 18: signal path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 19: timing diagram showing a write to reg0x09 with the value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . .3 4 figure 20: timing diagram showing a read from reg0x09; return ed value 0x0284 . . . . . . . . . . . . . . . . . . . . . . .34 figure 21: data output timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 22: serial host interface start condition timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 23: serial host interface stop condition timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 24: serial host interface data timing for write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 25: serial host interface data timing for read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 26: acknowledge signal timing after an 8-bit write to th e sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 27: acknowledge signal timing after an 8-bit read from the sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 28: quantum efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 29: image center offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 30: 48-pin plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_dslot.fm - rev. d 7/05 en 5 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor list of tables list of tables table 1: key performance parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 table 3: frame timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 table 4: register list and default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 5: reserved register list and default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 6: register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 table 7: standard resolutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 8: wide screen (16:9) resolutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 9: auto focus modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 10: strobe pulse output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 table 11: bin and skip mode resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 12: skip and bin modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 13: gain increment settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 14: dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 15: ac electrical characte ristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 table 16: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 6 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor general description (continued) general description (continued) figure 1: block diagram figure 2: typical configuration (connection) note: resistor value 1.5k is recommended, but may be great er for slower two-wire speed. a c tive-pixel s ensor (ap s ) array two-wire s erial interfa c e 10- b it data s yn c s i g nals timin g an d c ontrol c ontrol re g ister analo g pro c essin g ad c c lo c k 3.3v analo g 3 . 3 v a n a l o g 3.3v di g ital 3 . 3 v d i g i t a l d8 d 8 frame_valid f r a m e _ v a l i d d7 d 7 line_valid l i n e _ v a l i d pix c lk p i x c l k s trobe s t r o b e tri gg er t r i g g e r gs ht_ c tl g s h t _ c t l c lkin c l k i n d5 d 5 d 6 d 6 d0 d 0 d2 d 2 d3 d 3 d4 d 4 d9 d 9 d1 d 1 + mt9t001 m t 9 t 0 0 1 n c n c 9 tri gg er t r i g g e r 8 s tandby s t a n d b y 7 s data s d a t a 45 4 5 oe# o e # 13 1 3 sc lk s c l k 4 6 4 6 n c n c 11 1 1 re s et# r e s e t # 10 1 0 n c n c 14 1 4 gs ht_ c tl g s h t _ c t l 12 1 2 vaapix v a a p i x 1 a g nd a g n d 15 1 5 vaa v a a 1 6 1 6 n c n c 2 a g nd a g n d 18 1 8 a g nd a g n d 17 1 7 vdd v d d 4 d g nd d g n d 5 pix c lk p i x c l k 31 3 1 n c n c 6 vdd v d d 37 3 7 n c n c 3 d g nd d g n d 23 2 3 d8 d 8 35 3 5 d0 d 0 24 2 4 d5 d 5 32 3 2 d9 d 9 3 6 3 6 frame_valid f r a m e _ v a l i d 41 4 1 a g nd a g n d 48 4 8 d g nd d g n d 43 4 3 a g nd a g n d 47 4 7 n c n c 44 4 4 d 6 d 6 33 3 3 line_valid l i n e _ v a l i d 40 4 0 n c n c 42 4 2 d7 d 7 34 3 4 d g nd d g n d 38 3 8 d1 d 1 25 2 5 s trobe s t r o b e 39 3 9 d2 d 2 2 6 2 6 d3 d 3 27 2 7 vdd v d d 22 2 2 n c n c 19 1 9 a g nd a g n d 21 2 1 vaa v a a 20 2 0 d4 d 4 28 2 8 n c n c 30 3 0 c lkin c l k i n 29 2 9 + two-wire serial b us { .1 f 2.2 f 10 f 1.5k 1.5k 1k .01 f .1 f
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 7 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor general description (continued) figure 3: 48-pin plcc . table 1: pin descriptions pin numbers symbol type description 7 standby input standby: activates (high) standby mode, disables analog bias circuitry for power saving mode. 8 trigger input trigger: activates (hig h) snapshot sequence. 10 reset# input reset: activates (low) asynchronous re set of sensor. all registers assume factory defaults. 13 oe# input output enable: oe# when high, places outputs d out <0?9>, frame_valid, line_valid, pixclk, an d strobe into a tri-state configuration. 29 clkin input clock in: master clock into sensor (48 mhz maximum). 46 sclk input serial clock: clock for serial interface. 12 gsht_ctl input global shutter control. 45 s data i/o serial data: serial data bus, requires 1.5 k resistor to 3.3v for pull-up. 24, 25, 26, 27, 28, 32, 33, 34, 35, 36 d out <0?9> output data out: pixel data output bit 0, d out <9> (msb), d out <0> (lsb). 31 pixclk output pixel clock: pixel data ou tputs are valid during falling edge of this clock. frequency = (master clock). 39 strobe output strobe: output is pulsed high to indicate sensor reset operation of pixel array has completed. 40 line_valid output line valid: output is pulsed high during line of selectable valid pixel data (see reg0x20 for options). 41 frame_valid output frame valid: output is pulsed high during frame of valid pixel data. 1 2 3 4 5 6 48 47 4 6 45 44 43 19 20 21 22 23 24 25 2 6 27 28 29 30 7 8 9 10 11 12 13 14 15 1 6 17 18 42 41 40 39 38 37 3 6 35 34 33 32 31 s tandby tri gg er n c re s et# n c gs ht_ c tl oe# n c a g nd v aa a g nd a g nd n c frame_valid line_valid s trobe d g nd v dd d out <9> d out <8> d out <7> d out < 6 > d out <5> pix c lk n c v aa a g nd v dd d g nd d out <0> d out <1> d out <2> d out <3> d out <4> c lkin n c n c d g nd v dd n c n c vaapix a g nd a g nd sc lk s data n c d g nd
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 8 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor general description (continued) 1 vaapix supply analog pixel power: provide power su pply for pixel array, 3.3v 0.3v. 4, 22, 37 v dd supply digital power: provide power supply for digital block, 3.3v 0.3v. 5, 23, 38, 43 d gnd supply digital ground: provide isolat ed ground for digital block. 16, 20 v aa supply analog power: provide power supply for analog block, 3.3v 0.3v. 15, 17, 18, 21, 47, 48 a gnd supply analog ground: provide isolated grou nd for analog block and pixel array. 2, 3, 6, 9, 11,14,19, 30 42, 44 nc ? no connect: these pins must be left unconnected. table 1: pin descriptions (continued) pin numbers symbol type description
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 9 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor pixel data format pixel data format pixel array structure the mt9t001 pixel array is configured as 2,112 columns by 1,568 rows, as shown in figure 4. columns from 0 through 27 and fr om 2,085 through 2,111, and also rows from 0 through 15 and from 1,561 through 1,567 are optically black. these optical black col- umns and rows can be used to monitor the black level. the black row data is used inter- nally for the automatic black level adjustme nt. however, the black rows and columns can also be read out by setting reg0x20 (11) and reg0x1e (7), respectively. there are 2,057 columns by 1,545 rows of optically acti ve pixels, which provides a four-pixel boundary around the qxga (2,048 x 1,536) ima ge to avoid boundary effects during color interpolation and correction. the mt9t001 uses a bayer color pattern, as shown in figure 5. the even-numbered rows contain green and red color pixels, and odd-numbered rows contain blue and green color pixels. the even-numbered columns contain green and blue color pixels; odd-numbered columns contain red and green color pixels. figure 4: pixel array description figure 5: pixel color pattern detail (top right corner) (2111, 1567) 28 black columns 7 black rows 16 black rows (0, 0) 27 black columns qxga (2,048 x 1,536) + 4 pixel boundary for color correction + additional active column + additional active row = 2,057 x 1,545 active pixels 4 4 5 5 pixel (28, 16) black pixels column readout direction . . . . . . ... row readout direction g b g b g b r g r g r g g b g b g b r g r g r g g b g b g b r g r g r g g b g b g b
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 10 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor pixel data format output data format the mt9t001 image data is read out in a progressive scan. valid image data is sur- rounded by horizontal blanking and vertical blanking, as shown in figure 6. the amount of horizontal blanking and vertical blan king is programmable through reg0x05 and reg0x06, respectively. line_valid is high during the shaded region of the figure. frame_valid timing is described in ?output data timing? on page 10. figure 6: spatial illust ration of image readout output data timing the data output of the mt9t001 is synchronized with the pixclk output. when line_valid is high, one 10-bit pixel datum is output every pixclk period. the pixclk can be used as a clock to latch the data. d out data is valid on the falling edge of pixclk in default mode. the pixclk is high while master clock is high and then low while master clock is low. it is continuously enabled, even during the blank- ing period. the parameters in p, a, and q shown in figure 8 are defined in table 2. figure 7: timing example of pixel data p 0,0 p 0,1 p 0,2 .....................................p 0,n-1 p 0,n p 1,0 p 1,1 p 1,2 .....................................p 1,n-1 p 1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 p m-1,0 p m-1,1 .....................................p m-1,n-1 p m-1,n p m,0 p m,1 .....................................p m,n-1 p m,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 valid image horizontal blanking vertical blanking vertical/horizontal blanking line_valid pix c lk d out 9-d out 0 . . . . . . . . . . . . . . . . p 0 (9:0) p 1 (9:0) p 2 (9:0) p 3 (9:0) p 4 (9:0) p n-1 (9:0) p n (9:0) vali d ima g e data blankin g blankin g
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 11 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor pixel data format figure 8: row timi ng and frame_valid/ line_valid signals frame timing formulas table 2: frame timing parameter name equation (pixel clocks = master clock) default timing at 48 mhz r active rows ((reg0x03 + 1)/((reg0x22[2?0] + 1))) (rounded up to next even number) 1,536 pixel clocks = 32.0s a active columns ((reg0x04 + 1)/((reg0x23[2?0] + 1))) (rounded up to next even number) 2,048 pixel clocks = 42.67s p1 frame start blanking 1 331 if reg0x22[5?4] = 0, normal 673 if reg0x22[5?4] = 1, bin 2x 999 if reg0x22[5?4] = 2, bin 3x 331pixel clocks = 6.89s p2 frame start blanking 2 38 if reg0x23[5?4] = 0, normal 22if reg0x23[5?4] = 1, bin 2x 14 if reg0x23[5?4] = 2, bin 3x 38 pixel clocks = 0.79s p3 frame end blanking 3 reg0x05 (minimum reg0x05 value = 21) 142 pixel clocks = 2.96s q horizontal blanking p1 + p2 + p3 511 pixel clocks = 10.65s p4 shutter overhead reg0x0c + 316 x (reg0x23[5?4] +1) 316 pixel clocks = 6.58s t row rowtime the greater of : (a + q) or (p1+ p4) 2,559 pixel clocks = 53.31s v vertical blanking (reg0x06 + 1) x t row 66,534 pixel clocks = 1.39ms t fv frame valid time r x t row 3,930,624 pixel clocks = 81.89ms t frame total frame time the greater of: ((65536 x reg0x08 + reg0x09) x t row ) or ( t fv + v) 3,997,158 pixel clocks = 83.27ms p1+p2 a q a q ap3 . . . . . . . . . number of master clocks frame_valid line_valid
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 12 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor registers registers note: 1 = always 1 0 = always 0 d = programmable ? = read only *it is recommended that bit 14 be cleared **value 0x8040 is recommended table 3: register list and default values register # (hex) description data format (binary) default value (hex) 0x00 chip version 1011 0001 0000 0001 0x1621 0x01 row start 0000 00dd dddd ddd0 0x0014 0x02 column start 0000 0ddd dddd ddd0 0x0020 0x03 row size (window height ) 0000 00dd dddd ddd1 0x05ff 0x04 col size (window width) 0000 0ddd dddd ddd1 0x07ff 0x05 horizontal blanking 0000 00dd dddd dddd 0x008e 0x06 vertical blanking 00 00 00dd dddd dddd 0x0019 0x07 output control 0d0 0 0000 d0dd 00dd 0x0002 0x08 shutter width upper 0000 0000 0000 dddd 0x0000 0x09 shutter width dddd dddd dddd dddd 0x0619 0x0a pixel clock control dddd dddd dddd dddd 0x0000 0x0b restart 0000 0000 0000 000d 0x0000 0x0c shutter delay 0000 00dd dddd dddd 0x0000 0x0d reset 0000 0000 0000 000d 0x0000 0x1e read mode 1 1100 dddd 0100 0000* 0xc040** 0x20 read mode 2 ddd0 ddd0 0000 00dd 0x2000 0x21 read mode 3 0000 0000 0000 00dd 0x0000 0x22 row address mode 0ddd 0ddd 0ddd 0ddd 0x0000 0x23 column address mode 0000 0ddd 00dd 0ddd 0x0000 0x2b green1 gain 0ddd dddd 0d0d dddd 0x0008 0x2c blue gain 0ddd dddd 0d0d dddd 0x0008 0x2d red gain 0ddd dddd 0d0d dddd 0x0008 0x2e green2 gain 0ddd dddd 0d0d dddd 0x0008 0x32 test data 0000 0ddd dddd dd00 0x0000 0x35 global gain dddd dddd dddd dddd 0x0008 0x49 black level 0000 0ddd dddd dddd 0x00a8 0x4b row black default offset 0000 0ddd dddd dddd 0x0028 0x5d blc delta thresholds 0ddd dddd 0ddd dddd 0x2d13 0x5f cal threshold dddd dddd dddd dddd 0x231d 0x60 green1 offset 0000 000d dddd dddd 0x0020 0x61 green2 offset 0000 000d dddd dddd 0x0020 0x62 black level calibration dddd d000 0000 00dd 0x0000 0x63 red offset 0000 0ddd dddd dddd 0x0020 0x64 blue offset 0000 0ddd dddd dddd 0x0020 0xf8 chip enable/synchroni ze 0000 0000 0000 00dd 0x0001 0xff chip version 0001 0110 0010 0001 0x1621
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 13 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor registers table 4: reserved register list and default values register # (hex) description default value (hex) 0x27 reserved 0x0001 0x29 reserved 0x0401 0x30 reserved 0x0000 0x3c reserved 0x0010 0x3d reserved 0x0005 0x3e reserved 0x0003 0x3f reserved 0x0002 0x40 reserved 0x0005 0x41 reserved 0x0003 0x42 reserved 0x0003 0x43 reserved 0x0003 0x44 reserved 0x0003 0x45 reserved 0x0010 0x46 reserved 0x0010 0x47 reserved 0x0010 0x48 reserved 0x0010 0x4a reserved 0x0010 0x4c reserved 0x0030 0x4d reserved 0x0020 0x4e reserved 0x0010* 0x4f reserved 0x0014 0x50 reserved 0x8004 0x51 reserved 0x0002 0x52 reserved 0x8004 0x53 reserved 0x0002 0x54 reserved 0x0010 0x55 reserved 0x0010 0x56 reserved 0x0020 0x5b reserved 0x0007 0x5c reserved 0x071c 0x5e reserved 0x5364 0x65 reserved 0x0000 0x67 reserved 0x3fff 0x68 reserved 0x0000 0x69 reserved 0x0000 0x6a reserved 0x0000 0x6b reserved 0x0000 0x6c reserved 0x0000 0x6d reserved 0x0000 0x6e reserved 0x0000 0x70 reserved 0x00a3 0x71 reserved 0xa204 0x72 reserved 0xa006 0x73 reserved 0x260a 0x74 reserved 0x280c 0x75 reserved 0x520d
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 14 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor registers note: even reading some of thes e registers causes this part to go into an unknown state. *value 0x0020 is recommended 0x76 reserved 0x7054 0x77 reserved 0x0000 0x78 reserved 0x9c57 0x79 reserved 0x9e02 0x7a reserved 0x9e04 0x7b reserved 0x9e06 0x7c reserved 0xa006 0x7d reserved 0x5308 0x7e reserved 0x3208 0x7f reserved 0x7c52 0x80 reserved 0x004e 0x81 reserved 0x4e00 0x82 reserved 0x4c02 0x83 reserved 0x480c 0x84 reserved 0x4a0e 0x86 reserved 0x2e0c 0x87 reserved 0x0000 0x89 reserved 0x4c02 0x8a reserved 0x0000 0x8b reserved 0x4f0a 0x8c reserved 0x3a0a 0x90 reserved 0x061f 0x91 reserved 0x0000 0x92 reserved 0x0001 0xf1 reserved 0x0000 0xfa reserved 0x0000 0xfb reserved 0x0000 0xfc reserved 0x0000 0xfd reserved 0x0000 table 4: reserved register list and default values (continued) register # (hex) description default value (hex)
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 15 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor registers register description table 5: register descriptions register bit description chip id 0x00 15:0 this register is read-only and gives th e chip identificati on number: 0x1621. row start 0x01 10:0 first row to be read out ? default = 0x0014 (20), register value must be an even number. column start 0x02 11:0 first column to be read out ? default = 0x0020 (32), register va lue must be an even number. note: if column bin is enabled, the value must be a multiple of reg0x23 [5:4] + 1. row size 0x03 10:0 window height (number of rows - 1) ? default = 0x5ff (1535), register value must be an odd number. minimum value for 0x03 = 0x0001. column size 0x04 10:0 window width (number of columns - 1) ?d efault = 0x7ff (2047), regi ster value must be an odd number. minimum value for 0x04 = 0x0001. horizontal blank 0x05 10:0 horizontal blank ? default = 0x008e (142 pixels). minimum value = 0x0015 (21). vertical blank 0x06 10:0 vertical blank ?d efault = 0x0019 (25 rows). minimum value = 0x0003 (3). output control this register controls various featur es of the output format for the sensor. 0x07 0 synchronize changes. 0 = normal operation, update changes to registers th at affect image brightness (integration time, shutter delay, gain, horizontal and vertical blank, window size, row/column skip, or row mirror) at the next frame boundary. 1 = do not update any changes to these sett ings until this bit is returned to ?0.? 1 chip enable. 1 = normal operation. 0 = sensor readout is stopped and analog contro l signals are put in a state which draws minimal power. 6 override pixel data. 0 = normal operation. 1 = output programmed test data (see reg0x32). when set, a test pattern will be output instead of the sampled imag e from the sensor array. the value sent to the d out <9:0> pins will alternate between the te st data register (reg0x32) in even columns and the inverse of the test data register for odd column s. the output ?image? will have the same width, height, and frame rate as it would otherwise have. no digital processing (gain or offset) is applied to the data. when clear (the default), sampled pixel values are output normally. shutter width upper 0x08 15:0 the most significan t bits of the shutter width, which are combined with shutter width (reg0x09). the total shutter width is ther efore: (((shutter_width_upper) x 65536) + shutte r_width). this should allow a shutter width from about 50us to about 50s at default row time. shutter width 0x09 15:0 number of rows of integration, the exposure time; the time be tween when the rolling shutter resets a row and that row is read out, in rows. default = 0x0619 (1561). minimum value = 0x0001 (1).
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 16 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor registers pixel clock control 0x0a 15 invert pixel clock ? default = 0x00 (0) when set, line_valid, frame_valid, and data10_out are set up to th e rising edge of pixclk. when clear, they are set up to the falli ng edge. this is accomplished by inverting the pixclk output. 10:8 shift pixel clock ? default = 0x00 (0) two's complement value represen ting how far to shi ft the pixclk output pin relative to d out , in clkin cycles. positi ve values shift pixclk late r in time relative to d out (and thus relative to the internal array/datapath clock. no effect unle ss pixclk is divided by divide pixel clock. 6:0 divide pixel clock ? default = 0x00 (0) produces a pixclk that is divided by the value times two. the value must be a power of 2. this slows down the internal clock in the array control and datapath blocks, including pixel readout. it does not affect the two-wire seri al interface clock. a value of 0 corresponds to a pixclk with the same frequency as clk_in. a value of 1 means f_pixclk = (f_clk_in / 2); 2 means f_pixclk = (f_clk_in / 4); 64 means f_pi xclk = (f_clk_in / 128); etc. frame restart 0x0b 0 setting bit 0 to ?1? of reg0x0b causes the sens or to abandon the readou t of the current frame and restart from the first row. th is register automatically resets itself to 0x0000 after the frame restart. the first frame after this event is consid ered to be a "bad frame" (see description for reg0x20, bit 0). shutter delay 0x0c 10:0 shutter delay ? default = 0x0000 (0). this is the number of pixel clocks that the timing and control logic waits before assertin g the reset for a given row. reset 0x0d 0 setting this bit puts the sensor into reset mode, which sets the sensor to its default power-up state. clearing this bitresumes normal operation. read mode 1 0x1e 8 snapshot mode ? default is 0 (continuous mode). 1 = enable snapshot trigger signal can come from outside signal ( trigger pin 8 on the sensor) or from serial interface register restart, i.e . programming a ?1? to bit 0 of reg0x0b. 9 strobe enable ? default is 0 (no strobe signal). 1 = enable strobe (signal output from the sensor during the time all rows are integrating). see strobe width for mo re information. 10 strobe width ? default is 0 (strobe signal width at minimum length, one row of integration time, prior to line_valid going high). 1 = extend strobe width (strobe signal width exte nds to entire time all rows are integrating; shutter width must be >= ro w size + verti cal blanking). 11 strobe override ? default is 0 (strobe signal created by digital logic). 1 = override strobe signal (strobe signal is set high when this bit is set, low when this bit is set low. it is assumed that strobe enable is set to ?0? if strobe override is being used). read mode 2 0x20 0 no bad frames ? 1 = output all frames (including bad frames). 0 = default, only output good frames. a bad fr ame is defined as the first frame following a change to: window size or position, horizontal blanking, row or column skip, or mirroring. 9 1 = "continuous" line_valid (continue producing line_valid during vertical blanking). 0 = normal line_valid (default, no line_valid during vertical blank). 10 1 = line_valid = "c ontinuous" line_valid xor frame_valid. 0 = line_valid determined by bit 9 (default). table 5: register descriptions (continued) register bit description
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 17 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor registers read mode 3 0x21 0 global reset ? default = 0x0000 ? when set, snapshot mode ma kes use of the global reset ? that is, the entire array is released from reset simultaneously. ineffe ctive unless snapshot (reg0x1e[8]) is set. 1 use gsht_ctl ? default = 0x0000. when set, the leading edge of the gsht_ctl pad signal is used to start the shutter sequence in snapshot mode, and the trailing edge starts the re ad sequence. when clear, the leading edge of the trigger pad signal is used to initiate the shutter sequence, the traili ng edge of gsht_ctl starts the exposure, and the trailing edge of the trigger pad signal is used to start the strobe and readout. ineffective un less snapshot (reg0x1e[8]) and global reset are set. row address mode 0x22 2:0 row skip ? the number of row-pairs to skip for every row read. fo r example, ?0? means read every row pair. ?1? is skip 2x; 2 is skip 3x, etc. if row bin is non-zero, this should be set to the interval between the fi rst rows in each bin. for full binning, row skip equals row bin. 5:4 row bin ? the number of rows to be read per row ou tput minus one. for normal read out, this should be ?0.? for bin 2x, it should be ?1?; for bin 3x, it should be ?2.? column address mode 0x23 2:0 column skip ? the number of column -pairs to skip for every pair read. zero means read every column. ?1? means skip one pair for every pair read (skip 2x ); 2 means skip 2 pairs for every pair read (skip 3x) etc. 5:4 column bin ?t he number of columns to be addressed per column read ou t minus one. zero produces standard 1:1 read out. a value of ?1? produces bin 2x; ?2? would be bin 3x. note: column start address value must be a multiple of reg0x23 [5:4] + 1. green1 gain 0x2b 6:0 green1 analog gain ? default = 0x08 (8) = 1x gain. 14:8 green1 digital gain ? default = 0x00 (0) = 1x gain. blue gain 0x2c 6:0 blue analog gain ? default = 0x08 (8) = 1x gain. 14:8 blue digital gain ? default = 0x00 (0) = 1x gain. red gain 0x2d 6:0 red analog gain ? default = 0x08 (8) = 1x gain. 14:8 red digital gain ? default = 0x00 (0) = 1x gain. green2 gain 0x2e 6:0 green2 analog gain ? default = 0x08 (8) = 1x gain. 14:8 green2 digital gain ? default = 0x00 (0) = 1x gain. test data 0x32 11:2 test data ? the data inserted into the data path to produce test pattern when "use test data" (reg0x07, bit 6) is set. test data will be inserted for even columns, and the inverse will be inserted for odd columns. global gain 0x35 6:0 global analog gain ? default = 0x08 (8) = 1x gain. 14:8 global digital gain ? default = 0x00 (0) = 1x gain. this register can be used to set all four gains at once. when read, it returns the value stored in reg0x2b. black level 0x49 11:2 desired black level in image. table 5: register descriptions (continued) register bit description
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 18 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor registers black level calibration coarse thresholds 0x5d 6:0 low coarse threshold ? default = 0x13. this value should be less than low target threshold. see high coarse threshold below. 14:8 high coarse threshold ? default = 0x2d. if the average black va lue for a color is higher than this value or lower than low coarse threshold, the co arse mode is activated (if enabled). once the black level is between the high coarse threshold and the low coarse thresh old, the fine method is used. this value should be set no lower than high target threshold. black level calibration target thresholds 0x5f 6:0 thres_lo: lower thresh old for black level in units of adc lsbs ? default = 29. 14:8 thres_hi: upper thresh old for black level in units of adc lsbs ? default = 35. when the black value for a color is within these thresholds, it is considered to be on target. green1 offset 0x60 8:0 cal green1 ? two's complement representation of anal og offset correction value for green1. green2 offset 0x61 8:0 cal green2 ? two's complement representation of an alog offset correcti on value for green2. black level calibration 0x62 0 manual override of black level correction. 1 = override automatic black level co rrection with programmed values. 0 = normal operation (default). 1 force/disable black level calibration. 0 = enable offset corr ection (default). 1 = disable offset correction voltage (offset correction voltage = 0.0v). 12 recalculate black level ? 1 = start a new running digitally filter ed average for the black level (this is internally reset to ?0? imme diately), and do a rapid sweep to find the new starting point. 0 = normal operation (default). 13 lock red/blue calibration ? when set, only one calibration value is used for both red and blue channels. default is 0, set to ?0? at all times. note: gain for red and blue channels mu st be equal for setting to be effective. 14 lock green calibration ? when set, only one calibration valu e is used for both green1 and green2 channels. default is 0, set to ?0? at all times. note: gain for green1 and green2 channels mu st be equal for setting to be effective. red offset 0x63 8:0 cal red. two's complement representa tion of analog offset correction value for red. blue offset 0x64 8:0 cal blue. two's complement representa tion of analog offset co rrection value for blue. chip enable and two-wire serial interface write synchronize 0xf8 0 mirrors the functionali ty of reg0x07 bit 1, (chip enable). 1 = normal operation. 0 = stop sensor read out. when th is is returned to ?1,? sensor r ead out restarts at the starting row in a new frame. 1 mirrors the functiona lity of reg0x07 bit 0 (synchronize changes). 0 = normal operation, update changes to registers th at affect image brightness (integration time, integration delay, gain, horizontal and vertical blank, window size, row/column skip, or row/ column mirror) at the next frame boundary. 1 = do not update any changes to these se ttings until this bi t is returned to?0.? table 5: register descriptions (continued) register bit description
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 19 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor feature description feature description window control reg0x01, reg0x02, reg0x03, and reg0x04 these registers control the size of the window. window size the default programmed window size is 2,048 columns by 1,536 rows (2,048h x 1,536v). the control logic allows the flexibility to change the window size by programming reg0x03 and reg0x04. reg0x03 controls th e window height (number of rows) and reg0x04 controls the window width (number of columns). the value to be programmed in reg0x03 is the desired number of rows -1. the value to be programmed in reg0x04 is the desired number of columns -1. the minimum value for reg0x03 is 0x0001; for reg0x04, 0x0001. thus, the smallest win- dow size is two columns by two rows (2h x 2v). the value of reg0x03 and reg0x04 must be an odd number (there can only be even number of columns). the user can program the window size to be any format desired. ta ble 6 shows examples of register settings to achieve various resolutions and frame rates. note: for table 6 and table 7 above, the settings for reg0x05 (horizontal blanking) and reg0x06 (vertical blanking) are 21 and 15 respectively, while all of the registers are set to default. table 6: standard resolutions resolution frame rate column_size (reg0 x 04) row_size (reg0 x 03) shutter width (reg0 x 09) 2,048 x 1,536 qxga 12 fps 2,047 1,535 <1,552 1,600 x 1,200 uxga 20 fps 1,599 1,199 <1,216 1,280 x 1,024 sxga 27 fps 1,279 1,023 <1,040 1,024 x 768 xga 43 fps 1,023 767 <784 800 x 600 svga 65 fps 799 599 <616 640 x 480 vga 93 fps 639 479 <496 table 7: wide screen (16:9) resolutions resolution frame rate column_size (reg0 x 04) row_size (reg0 x 03) shutter width (reg0 x 09) 1,920 x 1,080 hdtv 18 fps 1,919 1,079 <1,096 1,280 x 720 hdtv 39 fps 1,279 719 <736
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 20 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor feature description electronic panning in addition to changing the window size, the user has the flexibility to change the loca- tion of the readout window. reg0x01 controls the first row to be read out and reg0x02 controls the first column to be read out. the default values are 0x0014 (decimal 20) for reg0x01 and 0x0020 (decimal 32) for reg0x02. th e first column to be read out must be an even number. reg0x01 and reg0x02, together with reg0x03 and reg0x04, allow the user to choose any segment of the imager array to be read out. this is especially beneficial when the user needs to zoom in on a small portion of th e image and perform an alysis on the image content. figure 9 shows some examples of the electronic panning/zoom-in and windowing capa- bilities of the sensor. blanking control reg0x05 and reg0x06 these registers control the blanking time in a row (called column fill-in or horizontal blanking) and between frames (vertical blanking). horizontal blanking is specified in terms of pixel clocks. vertical blanking is specified in terms of row readout times. the actual imager timing can be calculated using the equations given in table 2 on page 11. reg0x05 controls the horizontal blanking time in a row. the value is specified in terms of pixel clocks. default value of 0x008e for reg0x0 5 results in a horizontal blanking time of 511 pixel clocks. the minimum value for reg0 x05 is 21. thus, the minimum horizontal blanking time is 390 pixel clocks. reg0x06 controls the vertical blanking time in a row. the value is specified in terms of the number of rows. default value of 0x0019 for reg0x06 results in a vertical blanking time of 26-row time. frame time reg0x03, reg0x04, reg0x05, and reg0x06 total frame time in terms of pixel clocks can be obtained using the formula given in table 2 on page 11. the user can change the number of columns and rows read out, hor- izontal blanking and vertical blanking times to obtain different frame rates. high frame rate readout modes reg0x01, reg0x02, reg0x03, reg0x04, reg0x05, and reg0x06 in addition to having the flexibility to read out smaller standard formats, the sensor gives the user the option of reading out nonstandard formats. this is particularly useful if the user needs to zoom in on a particular se gment of the image to perform high-speed mathematical calculations (e.g., high-speed viewfinder or auto focus applications). in applications such as the auto focus mode, the user may need more horizontal resolu- tion than vertical. thus, the user can window down to the mid-section of the imager array by programming reg0x01 and reg0x03 to change the row start address and the window height. figure 10 is an example of how the user may want to window down to 2,048h x 512v from the default of 2,048h x 1,536v. see also table 8 for other auto focus mode resolutions.
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 21 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor feature description figure 9: windowing capabilities figure 10: windowing the user can change reg0x05 and reg0x06 to obtain the desired frame rate. also, the user may want to perform row skip modes to ob tain larger field of view if high-frequency vertical resolution is not critical. table 8: auto focus modes resolu- tion frame rate column_ size (reg0 x 04) row_ size (reg 0 x 03) horizontal_b lank (reg0 x 05) vertical_bl ank (reg0 x 06) row (reg 0 x 22) row_ skip (reg 0 x 22) column_ bin (reg0 x 23) column_ skip (reg0 x 23) 2,048 x 512 30 fps 2,047 1,535 22 1 2 2 0 0 2,048 x 256 60 fps 2,047 1,535 22 0 2 5 0 0 2,048 x 128 120 fps 2,047 1,023 34 14 1 7 0 0 (32, 20) (80, 912) a b c d (1327, 307) (1200, 180) (2048, 1536) (1007, 479) (568, 356) (1079, 867) window size reg0x01 reg0x02 reg0x03 reg0x04 2,048 x 1,536 0x0014 0x0020 0x05ff 0x07ff 128 x 128 0x00b4 0x04b0 0x007f 0x007f 512 x 512 0x0164 0x0238 0x01ff 0x01ff 400 x 96 0x0390 0x0050 0x018f 0x005f window a window b window c window d 2,048 1,536 512 row start = 20 (reg0x01 = 0x0014) row start = 356 (reg0x01 = 0x0164)
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 22 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor feature description pixel integration time control reg0x09 and reg0x0c the integration time of the pixel is the amount of time the pixels are set to collect charge generated from light. the user can change the integration time of the sensor by pro- gramming reg0x09. the value of reg0x09 sets the number of row time for integration. the sensor also supports sub-row integration time for fine control of pixel integration time. the formula for calculating the pixel integration time is (reference table 2 on page 11 for p1 description): t int = (65536 x reg0x08 + reg0x09) x t row -reg0x0c-p1+132 typically, the value of reg0x09 is limited to the number of rows per frame (which includes vertical blanking rows), such that the frame rate is not affected by the integra- tion time. however, if reg0x09 is increased beyond the total number of rows per frame, then additional blanking rows are added as needed. while the user can adjust the integration time to the desired value according to the aforementioned formula, not al l integration times may be desired under certain lighting conditions. if the light source has a flicker component, then the integration time needs to be set properly to av oid banding in the image. under 60hz flicker, the integration time must be a multiple of 1/120 of a second to avoid flicker. under 50hz flicker, the integration ti me must be a multiple of 1/100 of a second to avoid flicker. snapshot mode and flash control reg0x1e, strobe pin and trigger pin setting up for snapshot mode snapshot mode must be enabled before use by setting bit 8 = ?1? of reg0x1e. there are two important signals used for snapshot mode: trigger and strobe. the trigger signal initiates the start of a single frame ca pture and strobe is an output pulse that may be used to turn on a flash and/ or activate a mechanical shutter. triggering a snapshot the trigger signal required for starting a frame capture may be generated in the fol- lowing two ways: 1. external trigger pulse pin 8 is a digital input that may be used to supply an external trigger signal input. the snapshot operation begins after the trigge r pulse transitions from a high to low state. 2. trigger from register setting a second method for triggering a snapshot is by setting bit 0 = 1 of reg0x0b (restart). this register automatically returns bit 0 to ?0? after the trigger is initiated. this bit does not need to be reset by the user after use. strobe pulse output the strobe pulse must be enabled before use by setting reg0x1e [bit 9] = 1. the strobe signal has two options for pulse length and may be selected using reg0x1e [bit 10] as shown in table 9.
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 23 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor feature description after the trigger pulse has signaled a snap shot operation, each row of the imager array is reset in sequence to clear out an y accumulated signal. once each row of the imager is reset, the strobe pulse is output from the imager with a length dependent upon the characteristics described above. after the strobe pulse goes low, the imager waits 16 additional rows and then each row fr om the pixel array is read out. no strobe is generated unless the shutter width is grea ter than the output image height plus verti- cal blanking. global shutter rel ease snapshot mode reg0x1e and reg0x21 in addition to the standard snapshot mode , the mt9t001 has a global shutter release mode which may be combined with a mechanical shutter to achieve simultaneous exposure of all rows in the image. two global shutter modes are available: pr ogrammed exposure and bulb mode. in pro- grammed exposure mode, the exposure time is dictated by {reg0x08, reg0x09} (shutter width). in bulb mode, the trigger and gsht _ctl pins are used to achieve an arbi- trary exposure time. programmed exposure mode to use programmed exposure mode: 1. set up snapshot mode as normal (including any stro be preferences). 2. set reg0x21 (read mode 3) to 0x0003. 3. assert (transition low to high) the gsht_ctl pin to reset the array. this pin must remain high for 18820 pixclks. 4. negate (transition high to low) the gsht_ctl pin to begin the exposure. the exposure starts 1000 pixclks afte r the falling edge of gsht_ctl. note: unlike normal snapshot mode, reg0x0b (restart) may not be used to initiate the exposure in global shutter modes. 5. row readout begins automatically. the mechanical shutter should be closed before row read out begins. the trailing edge of strobe (if enabled) occurs ((65536 x reg0x08 + reg0x09) x t row + 2000) pixclks after the falling edge of gsht_ctl. readout of the active window starts the lesser of 16 x t row or (reg0x06 + 1) x t row later. bulb mode to use bulb mode: 1. set up snapshot mode as normal (including any stro be preferences). 2. set reg0x21 (read mode 3) to 0x0001. 3. assert (transition low to high) the gsht_ctl pin. 4. assert (transition low to high) the trigger pin to reset the array. this pin must remain high for at least 18,820 pixclks. 5. negate (transition high to low) the gsht_ctl pin to begin the exposure. the exposure starts 1,000 pixclks afte r the falling edge of gsht_ctl. table 9: strobe pulse output reg0 x 1e, bit 10 strobe pulse width 0 1 row time (default) 1 ((655326 x reg0x08 + reg0x09 ? r) -16) x t row - v
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 24 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor feature description note: unlike normal snapshot mode, reg0x0b (restart) may not be used to initiate the exposure in global shutter modes. 6. negate (transition high to low) the trigger pin to begin row read out. the mechanical shutter should be closed before row read out begins. the trailing edge of strobe (if enabled) occurs ((65536 x reg0x08 + reg0x09) x t row ) pixclks after the falling edge of trigger. read out of the active window starts the lesser of 16 x t row or (reg0x06 + 1) x t row later. in this mode, the shutter width (reg0x08, reg0x09) would normally be set to a low number, al lowing row readout to start immediately after the trailing edge of trigger. skip and bin modes row and column skip modes use subsampling to reduce the output resolution without reducing field-of-view. the mt9t001 also has row and column binning modes, which can reduce the impact of aliasing introduced by the use of skip modes. this is achieved by the averaging of two or three adjacent rows and columns (adjacent same-color pix- els). both 2x and 3x binning modes are su pported. rows and columns can be binned independently. note: column start address value must be a multiple of reg0x23 [5?4] + 1. to use binning mode, set reg0x22[5?4] (row bin) or reg0x23[5?4] (column bin) to the desired reduction minus 1, as would be done for skip mode. additionally, reg0x22[2?0] (column skip) must be set no less than reg0x22[5?4], and reg0x23[2?0] (row skip) must be set no less than reg0x23[5?4]. row and co lumn skip modes may be set higher than the corresponding binning modes to achieve greater reductions, but binning must be done. the different skip modes supported ar e between 2x and 8x in both column and row directions. the different binning modes supported are 2x and 3x. see table 11 for register bits controlling the different bin and skip modes. table 10: bin and ski p mode resolution resolu- tion frame rate column_ size (reg0 x 04) row_ size (reg 0 x 03) horizontal_ blank (reg0 x 05) vertical_ blank (reg0 x 06) row_ bin (reg 0 x 22) row_ skip (reg 0 x 22) column_ bin (reg0 x 23) column_ skip (reg0 x 23) 1,024 x 768 xga 34 fps 2,047 1,535 22 40 1 1 1 1 800 x 600 svga 50 fps 1,599 1,199 22 30 1 1 1 1 640 x 480 vga 48 fps 1,919 1,439 21 31 2 2 2 2 table 11: skip and bin modes register bit skip/bin modes readouts reg0x23 bit[2?0] bit[5?4] no column skip column skip 2x column skip 3x column skip 4x column skip 8x column bin 2x column bin 3x col0, col1, col2, col3, col4, col5, etc. col0, col1, col4, col5, col8, col9, etc. col0, col1, col16, col7, col12, col13 etc. col0, col1, col8, col9, col16, col17, etc. col0, col1, col16, col1 7, col32, col33, etc. binning of 2 adjacent same-c olor pixels in a 4x4 window binning of 3 pixel of each color plane in a 6x6 window
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 25 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor feature description note: column and row skip modes 1x through 8x are available on the mt 9t001. also, the read outs shown assume column start and row start addresses are both ?0?. figure 11: column ski p 2x; row skip 2x enabled reg0x22 bit[2?0] bit[5?4] no row skip row skip 2x row skip 3x row skip 4x row skip 8x row bin 2x row bin 3x row0, row1, row2, ro w3, row4, row5, etc. row0, row1, row4, ro w5, row8, row9, etc. row0, row1, row6, row7, row12, row13, etc. row0, row1, row8, row9, row16, row17, etc. row0, row1, row16, row1 7, row32, row33, etc. binning of 2 pixel of each color plane in a 4x4 window binning of 3 pixel of each color plane in a 6x6 window table 11: skip and bin modes (continued) register bit skip/bin modes readouts pixel (re g 0x01, re g 0x02) ... r g r g r g r g r g g b g b g b g b g b r g r g r g r g r g g b g b g b g b g b r g r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b g b r g r g r g r g r g g b g b g b g b g b . . .
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 26 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor feature description figure 12: column ski p 3x; row skip 3x enabled pixel (reg0x01, reg0x02) r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 27 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor feature description figure 13: column ski p 4x; row skip 4x enabled figure 14: column ski p 8x; row skip 8x enabled pixel (re g 0x01, re g 0x02) ... r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b . . . r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b pixel (re g 0x01, re g 0x02) ... r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b . . . r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 28 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor feature description figure 15: bin 2-to-1: 2,048h x 1, 536v (qxga) to 1, 024h x 768v (xga) note: grs = binning of 4 gr[s] in a 4 x 4 window; gbs = binning of 4 gb[s] in a 4 x 4 window. rs = binning of 4 r[s] in a 4 x 4 window; b[s] = binning of 4 b[s] in a 4 x 4 window. figure 16: bin 3-to-1: 2,048h x 1, 536v (qxga) to 640 h x 480v (vga) note: grs = binning of 9 gr[s] in a 6 x 6 window; gbs = binning of 9 gb[s] in a 6 x 6 window. rs = binning of 9 r[s] in a 6 x 6 window; bs = binning of b[s] in a 6 x 6 window. smaller format resolution reg0x01, reg0x02, reg0x03, reg0x04, reg0x05, reg0x06, reg0x22, and reg0x23 with the aforementioned flexible windowing capability of the sensor, the user is able to read out different resolution formats from default of qxga to uxga, sxga, xga, svga, vga, cif, qvga, qcif, etc. below are some examples of programmable register settings to obtain the estimated frame rates for the desired formats. the user can change the values of reg0x05 and reg0x06 to obtain different frame rates. the field of view of the image is reduced since the programmed settings effectively reduce the read out window to the specified settings without skipping any rows or col- umns. if the user only changes the register settings mentioned above without changing the row and column start address, the read out wind ow would start from that coordinate. to read out the center of the image or any portio n that is desired, the user would need to program reg0x01 and reg0x02, thus performing electronic panning. to maintain the same field of view while reducing the read out resolution, the user would need to perform row and column skip. for example, if the desired read out reso- lution needs to be xga (1,024h x 7,68v) instead of qxga (2,048h x 1,536v). to maintain the same field of view, the user can select co lumn skip 2x and row skip 2x modes. this gr r gr r b gb b gb gr r gr r b gb b gb grs rs bs gbs gr r gr r gr r b gb b gb b gb gr r gr r gr r b gb b gb b gb gr r gr r gr r b gb b gb b gb grs rs bs gbs
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 29 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor feature description effectively reduces the horizontal and vertical resolution by 2x for a factor of 4x reduc- tion in overall number of pixels that are re ad out. to perform this read out mode, the user would need to set the following: if the user sets reg0x03 = 0x02ff (768v rows), reg0x04 = 0x03ff (1,024h columns), and then enable column skip 2x and row skip 2x, the effective readout resolution is 512h x 384v. line_valid formats reg0x20 is used to control many aspects of th e readout of the sensor. by setting bit 9 and 10 of reg0x20 the line_valid signal can get three different output formats. the for- mats are shown in figure 17 when reading out four rows and two vertical blanking rows. in the last format the line_valid signal is the xor between the continuously line_valid signal and the frame_valid signal. figure 17: different line_valid formats reg0x03 = 0x05ff 1,536v rows reg0x04 = 0x07ff 2,048h columns reg0x23 bit[2:0]=1 column skip 2x?> 1,024h columns read out reg0x22 bit[2:0] = 1 row skip 2x ?> 768 rows read out default frame_valid line_valid continuously frame_valid line_valid xor frame_valid line_valid
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 30 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor feature description signal path the mt9t001 sensor analog signal path consis ts of the pixel array, the column sample and hold (s/h) circuitry, the programmable ga in stage, the analog offset correction and the analog-to-digital converter (adc). the reset and signal voltages from the pixe l are sampled onto the column sample and hold circuitry on a row-wise basis. after signal sampling is complete, the differential sig- nal (reset ? signal) is transferred to the programmable gain stage. after the gain stage, the differential signal goes through the analog offset correction cir- cuitry. the user can decide if a positive or negative offset or no offset needs to be added to the differential signal. the signal is then sampled onto the sample and hold circuitry of the adc before being digitized. figure 18: signal path gain settings reg0x2b, reg0x2c, reg0x2d, reg0x2e, and reg0x35 the analog programmable gain stage consists of two stages of gain circuitry that operate in a pipelined manner. the first stage of gain has programmable gain of 1 or 2 while the second stage of gain has programmable gain of 1 to 4 with steps of 0.125 for a maximum analog gain of 8. the gain settings can be independently adjusted for the colors of green1, blue, red, and green2 and are programmed through reg0x2b, reg0x2c, reg0x2d, and reg0x2e, respectively. the gain may also be adjusted globally through reg0x35. the first stage of gain is set by bit(6), while the second stage gain is set by bit(5 ? 0). the gain is individually controllable for each color in the bayer pattern as follows: analog gain < = 8: gain = (bit[6] + 1) x (bit[5:0] x 0.125) digital gain = 1 + bit[14:8]/8 total gain = analog gain x digital gain since bit[6] of the gain registers are multipli cative factors for the gain settings, there are alternative ways of achieving certain gains. some settings offer superior noise perfor- mance to others, despite the same overall gain, as shown in table 12. x + pixel volta g e analo g offset ( c olor-wise) 10- b it ad c di g ital g ain ( c olor-wise) analo g g ain ( c olor-wise) x + d out [9:0] di g ital offset ( c olor-wise) bla c k level c ali b ration -
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 31 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor feature description black level calibration reg0x5d, and reg0x5f the digitized black level of the mt9t001 sensor potentially varies with temperature or gain setting changes. the mt9t001 sensor allows the user the flexibility of automatic black level calibration or manual black level control. manual black level calibration reg0x60, reg0x61, reg0x62, reg0x63, and reg0x64 the programmable analog offset stage corrects for analog offset that might be present in the analog signal. the user would need to program reg0x62 appropriately to enable the analog offset correction. the analog offset settings can be independently adjusted for the colors of green1, green2, red and blue and are programmed through reg0x60, reg0x61, reg0x63 and reg0x64 respectively. bit[8] of reg0x60, reg0x61, reg0x63 and reg0x64 (these registers have two?s compleme nt representation) determines the sign of the analog offset. bit[8] = 1 makes the analog correction negative instead of positive. the lower 8 bits (bit[7:0]) determine the abso lute value of the analog offset to be cor- rected and bit[8] determines the sign of the co rrection. when bit[8] is ?1?, the sign of the correction is negative and vice versa. the an alog value of the correc tion relative to the analog gain stage can be determ ined from the following formula: analog offset = bit[8:0] x 1 lsb the 1 lsb value in the formula is an estimate amount. it deviates from 1 lsb with pro- cess variation. black level reg0x49 digital offset is applied such that the averag e black level of a frame in a resulting image equals the value of this register. this adjustment happens after black level calibration. reset this register is used to reset the sensor registers to their default, power-up state. to reset the mt9t001, first write a ?1? into bit 0 of this register to put the mt9t001 in reset mode, then write a ?0? into bit 0 to resume operation. another way to reset the sensor is through the reset# (pin 10) ? by pulling the reset# signal to 0v. the reset operation is an asynchronous reset and the sensor remains in reset as long as reset# signal = 0v. in both methods of reset, the sensor register settings returns to their default states. table 12: gain increment settings nominal gain increments recommended settings 1 to 4.000 0.125 0x0008 to 0x0020 4.25 to 8.00 0.25 0x0051 to 0x0060 9.0 to 128.0 1.0 0x0160 to 0x7860
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 32 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor serial bus description standby control and chip enable there are two steps required to put the sensor in standby mode: 1. through the two-wire serial interface prog ram reg0x07 bit[1] = 0. this stops the sen- sor readout and powers down analog circ uitry of the sensor. the sensor stays in standby mode until the user reprograms reg0x07 bit[1] = 1. 2. set standby (pin 7) to high. serial bus description registers are written to and read from the mt9t001 through the two-wire serial inter- face bus. the mt9t001 is a serial interface slave and is controlled by the serial clock (sclk), which is driven by the serial interface master. data is transferred into and out of the mt9t001 through the serial data (s data ) line. the s data line is pulled up to 3.3v off- chip by a 1.5k resistor. either the slave or master device can pull the s data line down? the serial interface protocol determines which device is allowed to pull the s data line down at any given time. protocol the two-wire serial defines several diffe rent transmission codes, as follows: ?a start bit ? the slave device 8-bit address ? a(n) (no) acknowledge bit ? an 8-bit message ?a stop bit sequence a typical read or write sequence begins by th e master sending a start bit. after the start bit, the master sends the slave device's 8-bi t address. the last bit of the address deter- mines if the request is a read or a write, wh ere a ?0? indicates a write and a ?1? indicates a read. the slave device acknowledges its address by sending an acknowledge bit back to the master. if the request was a write, the master then transfers the 8-bit register address to which a write should take place. the sl ave sends an acknowledge bit to indicate that the register address has been received. the master then tr ansfers the data eight bits at a time, with the slave sending an acknowledge bit after each eight bits. the mt9t001 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. after 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register address. the master stops writing by sending a start or stop bit. a typical read sequence is executed as follows. first the master sends the write-mode slave address and 8-bit register address, just as in the write request. the master then sends a start bit and the read-mode slave address. the master then clocks out the regis- ter data eight bits at a time. the master se nds an acknowledge bit after each 8-bit trans- fer. the register address is auto-incremented after every 16 bits is transferred. the data transfer is stopped when the master sends a no-acknowledge bit. bus idle state the bus is idle when both the data and cloc k lines are high. control of the bus is initi- ated with a start bit, and the bus is released with a stop bit. only the master can generate the start and stop bits.
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 33 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor serial bus description start bit the start bit is defined as a high-to-low transi tion of the data line while the clock line is high. stop bit the stop bit is defined as a low-to-high transi tion of the data line while the clock line is high. slave address the eight-bit address of a two-wire serial in terface device consists of seven bits of address and 1 bit of direction. a ?0? (0xba) in the lsb (least significant bit) of the address indicates write mode, and a ?1? (0xbb) indicates read mode. data bit transfer one data bit is transferred during each clock pulse. the serial interface clock pulse is provided by the master. the data must be stab le during the high period of the two-wire serial interface clock?it can only change wh en the serial clock is low. data is trans- ferred eight bits at a time, fo llowed by an acknowledge bit. acknowledge bit the master generates the acknowledge clock pu lse. the transmitter (which is the master when writing, or the slave when reading) re leases the data line, and the receiver indi- cates an acknowledge bit by pulling the data line low during the acknowledge clock pulse. no-acknowledge bit the no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. a no-acknowledge bit is used to terminate a read sequence.
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 34 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor two-wire serial interface sample write and read sequences two-wire serial interface samp le write and read sequences 16-bit write sequence a typical write sequence for writing 16 bits to a register is shown in figure 19. a start bit given by the master, followed by the write address, starts the sequence. the image sen- sor then gives an acknowledge bit and expects the register address to come first, fol- lowed by the 16-bit data. after each eight-bit transfer, the image sensor gives an acknowledge bit. all 16 bits must be written before the register is updated. after 16 bits are transferred, the register address is automa tically incremented so that the next 16 bits are written to the next register. the master stops writing by sending a start or stop bit. figure 19: timing diag ram showing a write to re g0x09 with the value 0x0284 16-bit read sequence a typical read sequence is shown in figure 20. first the master has to write the register address, as in a write sequence. then a start bit and the read address specifies that a read is about to happen from the register. the master then clocks out the register data eight bits at a time. the master sends an acknow ledge bit after each eight-bit transfer. the register address should be incremented after every 16 bits is transferred. the data trans- fer is stopped when the master sends a no-acknowledge bit. figure 20: timing diagra m showing a read from reg0x09; returned value 0x0284 sclk sdata start ack 0xba addr ack ack ack stop reg0x09 1000 0100 0000 0010 sclk sdata start ack 0xba addr 0xbb addr 0000 0010 reg0x09 ack ack ack stop 1000 0100 nack start
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 35 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor electrical specifications electrical specifications data output and propagation delays by default, the mt9t001 launches pixel data, frame_valid and line_valid with the rising edge of pixclk. the expectat ion is that the user captures d out [9:0], frame_valid and line_valid using the rising edge of pixclk. figure 21: data output timing diagram table 13: dc electrical characteristics (dc setup conditions: f clkin = 48 mhz, v dd = 3.3v, v aa = 3.3v, vaapix = 3.3v, t a = 25c) symbol definition condition min typ max units v dd core digital voltage 33.3 3.6 v v aa analog voltage 33.3 3.6 v vaapix pixel supply voltage 33.3 3.6 v v ih input high voltage 1.70 v v il input low voltage 1.45 v i in input leakage current no pull-up resistor; v in = v dd or d gnd ?5 5 a v oh output high voltage at specified i oh 3.3 v v ol output low voltage at specified i ol 00.3v i oh output high current at specified v oh 11.5 ma i ol output low current at specified v ol 12.5 ma i oz tri-state output leakage current 5a i dd digital operating current 0 lux, 48 mhz 20 23.0 ma i aa analog operating current 0 lux, 48 mhz 45.0 54.0 ma i aapix pixel supply current 0 lux, 48 mhz 4.0 5.0 ma i stdbyd digital standby current input clock disabled, 0 lux 0.2 2.0 a i stdbya analog standby current input clock disabled, 0 lux 0.2 2.0 a i stdbyda pixel standby current input clock disabled, 0 lux 0.1 1.0 a c lk pix c lk t r t f t c lkin d out 0-d out 9 frame vali d / line vali d xxx xxx xxx xxx xxx xxx note: frame_vali d lea d s line_vali d as d es c ri b e d in fi g ure 8 an d ta b le 3. note: frame_vali d trails line_vali d as d es c ri b e d in fi g ure 8 an d ta b le 3. t c p t pfl t pll t pd p 0 p 1 p 2 p n t t pfh t plh
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 36 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor electrical specifications . note: 1 stresses greater than those listed may cause permanent damage to th e device. this is a stress rating only, and fu nctional operation of the device at these or any other conditions above those indicated in the operational sections of this sp ecification is not implied. expo- sure to absolute maximum rati ng conditions for extended periods may affect reliability. table 14: ac electrical characteristics (ac setup conditions: f clkin = 48 mhz, v dd = 3.3v, v aa = 3.3v, vaapix = 3.3v, v ddpll , t a = 25c)) symbol definition condition min typ max unit f clkin input clock frequency 148mhz t clkin input clock period 1000 20.8 ns t pixclk period 1000 20.8 ns t r input clock rise time 4v/ns t f input clock fall time 4v/ns clock duty cycle 45 55 % t cp clkin to pixclk propagation delay 52 ns t pd pixclk to data valid 2ns t pfh pixclk to frame_valid high default 2 ns t plh pixclk to line_valid high default 2 ns t pfl pixclk to frame_valid low default 2 ns t pll pixclk to line_valid low default 2 ns c load load capacitance 30 pf table 15: absolute maximum ratings symbol parameter rating unit min max t op operating temperature 060c t st 1 storage temperature ?40 125 c
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 37 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor electrical specifications two-wire serial bus timing the two-wire serial bus operation requir es certain minimum master clock cycles between transitions. these are specified in the following diagrams in master clock cycles. figure 22: serial host inte rface start co ndition timing figure 23: serial host interface stop condition timing note: all timing are in un its of master clock cycle. figure 24: serial host interface data timing for write note: s data is driven by an off-chip transmitter. figure 25: serial host interface data timing for read note: s data is pulled low by the sensor, or allowed to be pulled high by a pull-up resistor off- chip. sclk 5 sdata 4 sclk 5 sdata 4 sclk 4 sdata 4 sclk 5 sdata
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 38 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor electrical specifications figure 26: acknowledge si gnal timing after an 8- bit write to the sensor figure 27: acknowledge si gnal timing after an 8- bit read from the sensor note: after a read, the master receiver must pull down s data to acknowledge receipt of data bits. when read sequence is complete, the master must generate a no acknowledge by leaving s data to float high. on the following cycle, a start or stop bit may be used. figure 28: quantum efficiency note: diagram not to scale. sclk sensor pulls down sdata pin 6 sdata 3 sclk sensor tri-states sdata pin (turns off pull down) 7 sdata 6 0 5 10 15 20 25 30 35 40 350 400 450 500 550 6 00 6 50 700 750 800 wavelen g th (nm) quantum effi c ien c y ( % ) blue g reen re d quantum effi c ien c y
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 39 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor electrical specifications figure 29: image center offset note: diagram not to scale. pixel array die c enter 0.078mm dark pixels pixel (0, 0) 7.802mm 7.721mm 0.934mm opti c al c enter
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo are tr ademarks of micron technology, inc. all other trademarks are the prope rty of their respective owners. this data sheet contains minimum and maximum limits specified over the complete power and temperature range for production devices. although considered fi nal, these specifications are subject to change, as further product development and data characterization sometimes occur. mt9t001 - 1/2-inch 3-megapixel digital image sensor electrical specifications 81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 40 ?2004 micron technology, inc. all rights reserved. figure 30: 48-pin plcc note: all dimensions in millimeters. seating plane 5.588 14.22 0.75 6.56 7.11 0.05 lid material: borosilicate glass 0.55 thickness mold compound: epoxy novolac substrate: plastic laminate 11.176 5.588 1.200 0.075 0.500 for reference only 1.050 0.075 1.016 typ 1.016 typ 11.176 48 1 47x 0.90 1.90 48x 0.50 7.11 0.05 6.56 14.22 0.75 13.00 ctr 13.00 ctr c l c l lead finish: gold plating, 0.50 microns minimum thickness 0.78 for reference only 2.25 for reference only 7.188 0.075 0.934 for reference only 6.176 0.075 c b optical area optical center die and package center maximum rotation of optical area relative to package edges b and c : 1o maximum tilt of optical area relative to seating plane a : 50 microns maximum tilt of optical area relative to top of cover glass d : 50 microns a d
81004bad/80ffb422 micron technology, inc., reserves the right to change products or specifications without notice. mt9t001_3100_ds_2.fm - rev. d 7/05 en 41 ?2004 micron technology, inc. all rights reserved. mt9t001 - 1/2-inch 3-megapixel digital image sensor revision history revision history rev d, 07/2005 ? remove preliminary designation ? updated table 1, key performance parameters, on page 1 ? updated table 3, register list and default values, on page 12 ? updated table 4, reserved register list and default values, on page 13 ? updated table 5, register descriptions, on page 15 ? updated table 13, dc electrical characteristics, on page 35 ? updated table 14, ac electrical characteristics, on page 36 ? add table 15, absolute maximum ratings, on page 36, and note ? updated page 33 (text, figure 21 replaced, figure 22 deleted) ? added figure 28, quantum efficiency, on page 38 ? removed die placement figure ? updated figure 30, 48-pin plcc, on page 40 rev c, preliminary 09/2004 ?added applications ? updated image center offset, figure 30 rev b, preliminary 03/2004 ? updated figure 29 ? added table 1, key performa nce parameters, on page 1 ? updated tables 2, 4, 5 and 6 rev a, verion 1.0, preliminary 12/2003 ? initial release of document

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